The present invention relates to a method of manufacturing a semiconductor device and, more specifically, to a method of fabricating an insulating film, using a dry-etching method, such as Reactive Ion Etching (RIE) and a method of manufacturing a semiconductor device using the above fabrication method.
A quantity of .mu. wave transistors is formed in the manner described below.
A p-type layer is formed on an n-type semiconductor substrate. A silicon oxide film and a silicon nitride film are sequentially deposited on the p-type layer. A resist film such as a Deep-UV resist or an UV resist is formed on the silicon nitride film. A resist of a predetermined pattern is formed, using a method for forming a thin resist film. The silicon nitride and oxide films are selectively etched, using the resist as a mask, by dry etching, such as by the RIE method. The resist is then removed. An emitter and a base are formed in the p-type layer, using the residual silicon oxide and nitride films. The electrodes of the emitter and the base are then formed. Note that the n-type semiconductor serves as a collector.
However, when this method is applied to the manufacture of semiconductor devices having submicron patterns (a pattern having a size of less than 1 .mu.m), the above manufacturing method has the following drawbacks:
(1) In order to form a submicron pattern, contact exposure using Deep-UV light is used. However, when the contact exposure method is used, if any substance is attached to a wafer, pattern size variations in the wafer are increased. Depending on the size of the attached substance, no pattern can be formed in an area of 1 to 2 cm around it.
(2) When a submicron pattern is to be formed, any mask alignment error must be less than 0.3 to 0.5 .mu.m. In other words, when one pattern is formed and then another pattrrn is formed thereon, reliability zone 3.sigma. of variations in the mask alignment is 3.sigma.=0.3 to 0.5 .mu.m, so that a high mask alignment accuracy is required between the two masks. However, it is difficult to obtain the above accuracy, using an existing mask aligner. In order to improve the mask alignment accuracy, a stepper has been considered and used in mass production recently. However, even when a stepper is used to form patterns, the limit of a pattern width is 1 .mu.m at a mass production level and the machine limit is about 0.8 .mu.m. Accordingly, only patterning with an improved accuracy of 1.0 to 1.2 .mu.m level can be performed, using the stepper.
(3) As for the RIE resistance of, for example, the Deep-UV resist, the Deep-UV resist has a relatively weak resistance, thereby considerably limiting the RIE conditions. Therefore, when the semiconductor wafers are actually manufactured, the throughput is decreased.
As has been described above, it is difficult to manufacture the semiconductor devices having submicron patterns, when using a conventional manufacturing method.